Clock and data recovery (CDR) is an important circuit in many high speed serial interface receivers. As the data at the receive end is not timed with the local clock (receiver side clock), the local clock will typically not be aligned with the centre of the data eye and so the data cannot be sampled/received directly using the local clock. A CDR circuit extracts the clock and data timing information from the received data and defines a sampling point which is closer to the centre of the data eye so that a correct data can be sampled/received.
A phase interpolator based CDR uses a PLL (phase locked loop) or DLL (delay locked loop) to implement a reference loop which accepts an input reference clock signal and produces a set of high speed clock reference phase signals spaced evenly across 360 degrees. These reference phases are then fed to a CDR loop which includes circuitry for selecting pairs of reference phases and interpolating between them to provide clocks for recovering the data from the data signal. Each time the system is started, a relatively long time period will be required to lock into the correct pair of reference phase signals.
The Low Latency Interface (LLI) is a point-to-point interconnect promulgated by the MIPI Alliance that allows two devices on separate chips to communicate as if a device attached to the remote chip is resident on the local chip. The connection between devices is at their respective interconnect level, e.g. OCP (on-chip protocol), AMBA® protocols, using memory mapped transactions. A LLI Link is a bidirectional interface allowing either device to initiate transactions. LLI provides a low latency interface for internal or external devices (e.g. DRAM) between two integrated circuits (ICs). The bandwidth is scalable from 2.9 Gb/sec over one differential signal pair, called a lane, to 17 Gb/sec over 6 lanes—in each direction. Differential serial data is driven and received by Type 1 M-PHY's defined by the PHY (Physical layer) working group of the MIPI Alliance and is intended to handle data rates in excess of 1000 Mbits/sec. M-PHY is named after the Roman number “M” for 1000. Each data lane has an M-PHY at both ends. The analog PHY's are managed by an LLI controller on their respective ICs, and those controllers interface to the rest of the IC.
Other features of the present embodiments will be apparent from the accompanying drawings and from the detailed description that follows.